The Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is a transistor that can be widely used in digital circuits and analog circuits.
FIG. 10 is a cross-sectional view of a conventional MOSFET device. As illustrated in FIG. 10, the MOSFET comprises a substrate 100, a source/drain region 110, a source/drain extension region 111, a gate stack and a spacer 240. Optionally, the MOSFET further comprises a shallow trench 120 for isolating adjacent MOSFET structures. The gate stack is formed on the substrate 100, and comprises a gate dielectric layer 210, a gate 220 and a cap layer 230. The source/drain region 110 is formed in the substrate 100 and located at both sides of the gate stack. The source/drain extension region 111 extends from the source/drain region 110 to approach the gate stack, with a thickness less than that of the source/drain region 110. The spacer 240 is located on sidewalls of the gate stack and covers the source/drain extension region 111. A contact layer 300 (beneficial to the reduction of the contact resistance) is provided on the source/drain region 110. For a Si-containing substrate, the contact layer 300 may be a metal silicide layer. In the following, the description is made by taking the Si-containing substrate as an example, and the contact layer is referred to as the metal silicide layer.
The contact layer is beneficial to the reduction of the contact resistance of the source/drain region. The Si-based semiconductor is taken as an example. As illustrated in FIG. 11, in a deep submicron CMOS device, the conventional materials of the metal silicide layer are TiSi2 and CoSi2. With a further decrease of the device size, especially when the technology node reaches about 90 nm, 65 nm and beyond, it is impossible for TiSi2 and CoSi2 to meet the requirement of lower contact resistance. At the technology node of about 65 nm and beyond, NiSi replaces TiSi2 and CoSi2 and becomes a new generation material of the contact layer. In Hiroshi Iwai, etc., “NiSi salicide technology for scaled CMOS” published in Microelectronic Engineering, the application of the NiSi self-aligned silicide technology in the CMOS process is introduced in detail. As compared with metal silicide such as TiSi2 and CoSi2, NiSi has advantages of low formation temperature (˜400° C.), low silicon consumption in a silicification process and lower contact resistance. By adding a right amount of appropriate metal, such as Pt, and taking the Ni alloy silicide as the contact layer, the thermal stability of NiSi that forms a pseudo-binary solid-state solution can be improved, so that the device acquires an optimum performance.
The formation process of NiSi is different from that of TiSi2 and CoSi2, etc. During the silicification process, Ni diffuses into the silicon to form NiSi, while TiSi2 etc. is formed by Si atoms diffusing into the metal to generate silicide. In the silicon, Ni has a higher diffusion coefficient than Ti, Co or Pt, etc. When Ni laterally diffuses into the channel region, a silicide layer is formed in the channel accordingly. As a result, shorts may easily occur in the channel, and cause failure of the semiconductor device.
Therefore, it is a problem urgently to be solved to reduce the Ni diffusion while the contact resistance meets the product requirement.